It is well known to form semiconductor devices and/or ICs where the principal device current or other significant device current is carried through the semiconductor to the back side of the substrate on or in which the SC device or IC is formed. The device may be a stand-alone device such as a power device, or part of an integrated circuit (IC) formed in or on a common semiconductor or other substrate. Vertical channel field effect transistors (FETs) and vertical channel metal-oxide field effect transistors (MOSFETs) such as trench-FETs, trench-gate MOSFETs, U-channel MOSFETs (UMOS), V-type MOSFETs (VMOS), and T-type MOSFETS (TMOS) are non-limiting examples of devices in which the principal device current flows from an active device region near an upper device surface through the bulk of the semiconductor substrate to a backside of the device where it is extracted. In other configurations applicable to various small signal as well as power semiconductor devices, low resistance coupling to back-side contacts, conductors and/or interconnections may be used for a variety of purposes. The abbreviations MOS, MOSFET, VMOS, UMOS, TMOS and the like are intended to include devices whose dielectric layers may include materials other than oxides.
FIG. 1 is a simplified schematic cross-sectional view of generalized semiconductor (SC) element 20 in which principal current I flows through semiconductor substrate 22 to back-side 222 of device 20. The active portions (e.g., devices 21) of element 20 are formed within region 24 primarily in upper layer 23, often an epi-layer, near front surface 25. Devices 21 within region 24 may be any type of SC device. First principal contact 26 is generally made to the active portion of device(s) 21 in region 24 on upper surface 25. Terminal 261 is provided to contact 26. Control contact 28 is generally also made to the active device portion of device(s) 21 within region 24 on upper surface 25. Terminal 281 is provided to contact 28. Backside contact 224 is provided on back surface 222 of substrate 22 thereby forming a second principal contact to element 20. Terminal 225 is provided to contact 224. Resistance Ra represents the internal resistance of active device(s) 21 within region 24 and resistance Rs represents the resistance of substrate 22. Principal current I flows through resistances Ra and Rs when element 20 is in the ON state. Accordingly, neglecting contact, metal and wires resistances, the ON-resistance of element 20 is given substantially by Ron=Ra+Rs.
It has been found that a significant portion, sometimes a dominant portion, of the series ON-resistance Ron of element 20 is attributable to substrate resistance Rs. Various attempts have been made in the past to reduce Rs, as for example, thinning the substrate or etching depressions in the back side of the substrate and filling them with highly conductive metals such as copper. However, none of these prior art approaches to reducing Rs has proved completely satisfactory. For example: (i) it is often difficult to etch high aspect ratio AR (AR=depth/width) vias or trenches in thick wafers with the result that achievable vias or trenches occupy undesirably large amounts of chip area; and/or (ii) substantial thinning of the substrates to facilitate forming narrow or small area vias can make the semiconductor wafers or die on or in which the SC devices or ICs are being fabricated extremely fragile and difficult to handle in volume manufacturing without undue breakage loss; and/or (iii) use of plated copper vias or trenches in the wafer backside as has been attempted in the prior art can introduce stress in the wafer or die that can adversely affect device properties and stability. Accordingly, there is an ongoing need to provide more robust fabrication methods and structures for devices and ICs employing back-side coupling and contacts, especially those incorporating power devices, that can provide lower Rs while avoiding or minimizing the foregoing and other limitations of the prior art.